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| 5v, 3.3v, isr? high-performance cplds ultra37000? cpld family cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 document #: 38-03007 rev. ** revised march 15, 2001 features in-system reprogrammable ? (isr ? ) cmos cplds ? jtag interface for reconfigurability ? design changes don ? t cause pinout changes ? design changes don ? t cause timing changes high density ? 32 to 512 macrocells ? 32 to 264 i/o pins ? 5 dedicated inputs including 4 clock pins simple timing model ? no fanout delays ? no expander delays ? no dedicated vs. i/o pin delays ? no additional delay through pim ? no penalty for using full 16 product terms ? no delay for steering or sharing product terms 3.3v and 5v versions pci compatible [1] programmable bus-hold capabilities on all i/os intelligent product term allocator provides: ? 0 to 16 product terms to any macrocell ? product term steering on an individual basis ? product term sharing among local macrocells flexible clocking ? 4 synchronous clocks per device ? product term clocking ? clock polarity control per logic block consistent package/pinout offering across all densities ? simplifies design migration ? same pinout for 3.3v and 5.0v devices packages ? 44 to 400 leads in plcc, clcc, pqfp, tqfp, cqfp, bga, and fine-pitch bga packages general description the ultra37000 ? family of cmos cplds provides a range of high-density programmable logic solutions with unparalleled system performance. the ultra37000 family is designed to bring the flexibility, ease of use, and performance of the 22v10 to high-density cplds. the architecture is based on a number of logic blocks that are connected by a programmable inter- connect matrix (pim). each logic block features its own prod- uct term array, product term allocator, and 16 macrocells. the pim distributes signals from the logic block outputs and all in- put pins to the logic block inputs. all of the ultra37000 devices are electrically erasable and in- system reprogrammable (isr), which simplifies both design and manufacturing flows, thereby reducing costs. the isr fea- ture provides the ability to reconfigure the devices without hav- ing design changes cause pinout or timing changes. the cypress isr function is implemented through a jtag-compli- ant serial interface. data is shifted in and out through the tdi and tdo pins, respectively. because of the superior routability and simple timing model of the ultra37000 devices, isr allows users to change existing logic designs while simultaneously fixing pinout assignments and maintaining system perfor- mance. the entire family features jtag for isr and boundary scan, and is compatible with the pci local bus specification, meet- ing the electrical and timing requirements. the ultra37000 family features user programmable bus-hold capabilities on all i/os. ultra37000 5.0v devices the ultra37000 devices operate with a 5v supply and can sup- port 5v or 3.3v i/o levels. v cco connections provide the ca- pability of interfacing to either a 5v or 3.3v bus. by connecting the v cco pins to 5v the user insures 5v ttl levels on the outputs. if v cco is connected to 3.3v the output levels meet 3.3v jedec standard cmos levels and are 5v tolerant. these devices require 5v isr programming. ultra37000v 3.3v devices devices operating with a 3.3v supply require 3.3v on all v cco pins, reducing the device ? s power consumption. these devices support 3.3v jedec standard cmos output levels, and are 5v tolerant. these devices allow 3.3v isr programming. note: 1. due to the 5v-tolerant nature of 3.3v device i/os, the i/os are not clamped to v cc , pci v ih =2v.
ultra37000 ? cpld family document #: 38-03007 rev. ** page 2 of 67 selection guide 5.0v selection guide general information device macrocells dedicated inputs i/o pins speed (t pd ) speed (f max ) cy37032 32 5 32 6 200 cy37064 64 5 32/64 6 200 cy37128 128 5 64/128 6.5 167 cy37192 192 5 120 7.5 154 cy37256 256 5 128/160/192 7.5 154 cy37384 384 5 160/192 10 118 cy37512 512 5 160/192/264 10 118 speed bins device 200 167 154 143 125 100 83 66 cy37032 x x x cy37064 x x x cy37128 x x x cy37192 x x x cy37256 x x x cy37384 x x cy37512 x x x device-package offering & i/o count device 44- lead tqfp 44- lead plcc 44- lead clcc 84- lead plcc 84- lead clcc 100- lead tqfp 160- lead tqfp 160- lead cqfp 208- lead pqfp 208- lead cqfp 256- lead bga 352- lead bga cy37032 37 37 cy37064 37373769 69 cy37128 69 69 69 133 cy37192 125 cy37256 133 133 165 197 cy37384 165 197 cy37512 165 165 197 269 ultra37000 ? cpld family document #: 38-03007 rev. ** page 3 of 67 3.3v selection guide general information device macrocells dedicated inputs i/o pins speed (t pd ) speed (f max ) cy37032v 32 5 32 8.5 143 cy37064v 64 5 32/64 8.5 143 cy37128v 128 5 64/80/128 10 125 cy37192v 192 5 120 12 100 cy37256v 256 5 128/160/192 12 100 cy37384v 384 5 160/192 15 83 cy37512v 512 5 160/192/264 15 83 speed bins device 200 167 154 143 125 100 83 66 cy37032v x x cy37064v x x cy37128v xx x cy37192v xx cy37256v xxx cy37384v xx cy37512v xxx shaded areas indicate preliminary speed bins. device-package offering & i/o count device 44- lead tqfp 44- lead plcc 44- lead clcc 48- lead fbga 84- lead plcc 84- lead clcc 100- lead tqfp 100- lead fbga 160- lead tqfp 160- lead cqfp 208- lead pqfp 208- lead cqfp 256- lead bga 256- lead fbga 352- lead bga 400- lead fbga cy37032v 37 37 37 cy37064v3737373769 6969 cy37128v 69 69 69 85 133 cy37192v 125 cy37256v 133 133 165 197 197 cy37384v 165 197 cy37512v 165 165 197 269 269 ultra37000 ? cpld family document #: 38-03007 rev. ** page 4 of 67 architecture overview of ultra37000 family programmable interconnect matrix the programmable interconnect matrix (pim) consists of a completely global routing matrix for signals from i/o pins and feedbacks from the logic blocks. the pim provides extremely robust interconnection to avoid fitting and density limitations. the inputs to the pim consist of all i/o and dedicated input pins and all macrocell feedbacks from within the logic blocks. the number of pim inputs increases with pin count and the number of logic blocks. the outputs from the pim are signals routed to the appropriate logic blocks. each logic block receives 36 in- puts from the pim and their complements, allowing for 32-bit operations to be implemented in a single pass through the device. the wide number of inputs to the logic block also im- proves the routing capacity of the ultra37000 family. an important feature of the pim is its simple timing. the prop- agation delay through the pim is accounted for in the timing specifications for each device. there is no additional delay for traveling through the pim. in fact, all inputs travel through the pim. as a result, there are no route-dependent timing param- eters on the ultra37000 devices. the worst-case pim delays are incorporated in all appropriate ultra37000 specifications. routing signals through the pim is completely invisible to the user. all routing is accomplished by software ? no hand routing is necessary. warp ? and third-party development packages automatically route designs for the ultra37000 family in a mat- ter of minutes. finally, the rich routing resources of the ultra37000 family accommodate last minute logic changes while maintaining fixed pin assignments. logic block the logic block is the basic building block of the ultra37000 architecture. it consists of a product term array, an intelligent product-term allocator, 16 macrocells, and a number of i/o cells. the number of i/o cells varies depending on the device used. refer to figure 1 for the block diagram. product term array each logic block features a 72 x 87 programmable product term array. this array accepts 36 inputs from the pim, which originate from macrocell feedbacks and device pins. active low and active high versions of each of these inputs are generated to create the full 72-input field. the 87 product terms in the array can be created from any of the 72 inputs. of the 87 product terms, 80 are for general-purpose use for the 16 macrocells in the logic block. four of the remaining seven product terms in the logic block are output enable (oe) product terms. each of the oe product terms controls up to eight of the 16 macrocells and is selectable on an individual macrocell basis. in other words, each i/o cell can select be- tween one of two oe product terms to control the output buffer. the first two of these four oe product terms are available to the upper half of the i/o macrocells in a logic block. the other two oe product terms are available to the lower half of the i/o macrocells in a logic block. the next two product terms in each logic block are dedicated asynchronous set and asynchronous reset product terms. the final product term is the product term clock. the set, reset, oe and product term clock have polarity control to realize or functions in a single pass through the array. figure 1. logic block with 50% buried macrocells i/o cell 0 product term allocator i/o cell 14 macro- cell 0 macro- cell 1 macro- cell 14 0 ? 16 product terms 72 x 87 product term array 80 36 8 16 to pim from pim 7 3 2 macro- cell 15 2 to cells 2, 4, 6 8, 10, 12 0 ? 16 product terms 0 ? 16 product terms 0 ? 16 product terms ultra37000 ? cpld family document #: 38-03007 rev. ** page 5 of 67 low-power option each logic block can operate in high-speed mode for critical path performance, or in low-power mode for power conserva- tion. the logic block mode is set by the user on a logic block by logic block basis. product term allocator through the product term allocator, software automatically dis- tributes product terms among the 16 macrocells in the logic block as needed. a total of 80 product terms are available from the local product term array. the product term allocator pro- vides two important capabilities without affecting performance: product term steering and product term sharing. product term steering product term steering is the process of assigning product terms to macrocells as needed. for example, if one macrocell requires ten product terms while another needs just three, the product term allocator will ? steer ? ten product terms to one macrocell and three to the other. on ultra37000 devices, prod- uct terms are steered on an individual basis. any number be- tween 0 and 16 product terms can be steered to any macrocell. note that 0 product terms is useful in cases where a particular macrocell is unused or used as an input register. product term sharing product term sharing is the process of using the same product term among multiple macrocells. for example, if more than one output has one or more product terms in its equation that are common to other outputs, those product terms are only programmed once. the ultra37000 product term allocator al- lows sharing across groups of four output macrocells in a vari- able fashion. the software automatically takes advantage of this capability ? the user does not have to intervene. note that neither product term sharing nor product term steer- ing have any effect on the speed of the product. all worst-case steering and sharing configurations have been incorporated in the timing specifications for the ultra37000 devices. ultra37000 macrocell within each logic block there are 16 macrocells. macrocells can either be i/o macrocells, which include an i/o cell which is associated with an i/o pin, or buried macrocells, which do not connect to an i/o. the combination of i/o macrocells and buried macrocells varies from device to device. buried macrocell figure 2 displays the architecture of buried macrocells. the buried macrocell features a register that can be configured as combinatorial, a d flip-flop, a t flip-flop, or a level-triggered latch. the register can be asynchronously set or asynchronously re- set at the logic block level with the separate set and reset prod- uct terms. each of these product terms features programma- ble polarity. this allows the registers to be set or reset based on an and expression or an or expression. clocking of the register is very flexible. four global synchro- nous clocks and a product term clock are available to clock the register. furthermore, each clock features programmable po- larity so that registers can be triggered on falling as well as rising edges (see the clocking section). clock polarity is cho- sen at the logic block level. the buried macrocell also supports input register capability. the buried macrocell can be configured to act as an input reg- ister (d-type or latch) whose input comes from the i/o pin as- sociated with the neighboring macrocell. the output of all bur- ied macrocells is sent directly to the pim regardless of its configuration. i/o macrocell figure 2 illustrates the architecture of the i/o macrocell. the i/o macrocell supports the same functions as the buried mac- rocell with the addition of i/o capability. at the output of the macrocell, a polarity control mux is available to select active low or active high signals. this has the added advantage of allowing significant logic reduction to occur in many applica- tions. the ultra37000 macrocell features a feedback path to the pim separate from the i/o pin input path. this means that if the macrocell is buried (fed back internally only), the associated i/o pin can still be used as an input. bus hold capabilities on all i/os bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device ? s performance. as a latch, bus-hold maintains the last state of a pin when the pin is placed in a high-impedance state, thus reducing system noise in bus-in- terface applications. bus-hold additionally allows unused de- vice pins to remain unconnected on the board, which is partic- ularly useful during prototyping as designers can route new signals to the device without cutting trace connections to v cc or gnd. for more information, see the application note ? un- derstanding bus-hold ? a feature of cypress cplds. ? programmable slew rate control each output has a programmable configuration bit, which sets the output slew rate to fast or slow. for designs concerned with meeting fcc emissions standards the slow edge provides for lower system noise. for designs requiring very high perfor- mance the fast edge rate provides maximum system perfor- mance. ultra37000 ? cpld family document #: 38-03007 rev. ** page 6 of 67 f figure 2. i/o and buried macrocells figure 3. input macrocell c2 c3 decode c2 c3 decode 0 1 2 3 o c6 c5 ? 0 ? ? 1 ? 0 1 o d/t/l q r p 0 1 2 3 o c0 0 1 o c4 feedback to pim feedback to pim block reset 0 ? 16 terms i/o macrocell i/o cell from ptm 0 1 o d/t/l q r p from ptm 1 o c7 feedback to pim buried macrocell 0 asynchronous product 0 ? 16 terms product c1 4 0 1 2 3 q 4 c24 c0 c1 c24 c25 c25 4 synchronous clocks (clk0,clk1,clk2,clk3) 1 asynchronous clock(ptclk) block preset asynchronous fast slow c26 slew 0 1 0 1 0 1 0 1 oe0 oe1 0 1 2 3 o c12 c13 to pim d q d q d q le input pin 0 1 2 o c10 from clock polarity muxes 3 c11 ultra37000 ? cpld family document #: 38-03007 rev. ** page 7 of 67 clocking each i/o and buried macrocell has access to four synchronous clocks (clk0, clk1, clk2 and clk3) as well as an asynchro- nous product term clock ptclk. each input macrocell has access to all four synchronous clocks. dedicated inputs/clocks five pins on each member of the ultra37000 family are desig- nated as input-only. there are two types of dedicated inputs on ultra37000 devices: input pins and input/clock pins. figure 3 illustrates the architecture for input pins. four input options are available for the user: combinatorial, registered, double-registered, or latched. if a registered or latched option is selected, any one of the input clocks can be selected for control. figure 4 illustrates the architecture for the input/clock pins. like the input pins, input/clock pins can be combinatorial, reg- istered, double-registered, or latched. in addition, these pins feed the clocking structures throughout the device. the clock path at the input has user-configurable polarity. product term clocking in addition to the four synchronous clocks, the ultra37000 fam- ily also has a product term clock for asynchronous clocking. each logic block has an independent product term clock which is available to all 16 macrocells. each product term clock also supports user configurable polarity selection. timing model one of the most important features of the ultra37000 family is the simplicity of its timing. all delays are worst case and sys- tem performance is unaffected by the features used. figure 5 illustrates the true timing model for the 167-mhz devices in high speed mode. for combinatorial paths, any input to any output incurs a 6.5-ns worst-case delay regardless of the amount of logic used. for synchronous systems, the input set- up time to the output macrocells for any input is 3.5 ns and the clock to output time is also 4.0 ns. these measurements are for any output and synchronous clock, regardless of the logic used. the ultra37000 features: no fanout delays no expander delays no dedicated vs. i/o pin delays no additional delay through pim no penalty for using 0 ? 16 product terms no added delay for steering product terms no added delay for sharing product terms no routing delays no output bypass delays the simple timing model of the ultra37000 family eliminates unexpected performance penalties. jtag and pci standards pci compliance 5v operation of the ultra37000 is fully compliant with the pci local bus specification published by the pci special interest group. the 3.3v products meet all pci requirements except for the output 3.3v clamp, which is in direct conflict with 5v tolerance. the ultra37000 family ? s simple and predictable tim- ing model ensures compliance with the pci ac specifications independent of the design. figure 4. input/clock macrocell 0 1 2 3 o c10c11 to pim d q d q d q le input/clock pin 0 1 2 o from clock clock pins 0 1 o c12 to clock mux on all input macrocells to clock mux in each 3 0 1 clock polarity mux one per logic block for each clock input polarity input logic block c8 c9 c13, c14, c15 or c16 o figure 5. timing model for cy37128 combinatorial signal registered signal d,t,l o clock input input output output t s = 3.5 ns t co = 4.5 ns t pd = 6.5 ns ultra37000 ? cpld family document #: 38-03007 rev. ** page 8 of 67 ieee 1149.1 compliant jtag the ultra37000 family has an ieee 1149.1 jtag interface for both boundary scan and isr. boundary scan the ultra37000 family supports bypass, sample/preload, ex- test, idcode, and usercode boundary scan instructions. the jtag interface is shown in figure 6 . in-system reprogramming (isr) in-system reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. this combination means design changes during debug or field upgrades do not cause board respins. the ultra37000 family implements isr by providing a jtag compliant interface for on-board programming, robust routing resources for pinout flexibility, and a simple timing model for consistent system performance. development software support warp ? warp is a state-of-the-art compiler and complete cpld design tool. for design entry, warp provides an ieee-std-1076/1164 vhdl text editor, an ieee-std-1364 verilog text editor, and a graphical finite state machine editor. it provides optimized syn- thesis and fitting by replacing basic circuits with ones pre-op- timized for the target device, by implementing logic in unused memory and by perfect communication between fitting and synthesis. to facilitate design and debugging, warp provides graphical timing simulation and analysis. warp professional ? warp professional contains several additional features. it pro- vides an extra method of design entry with its graphical block diagram editor. it allows up to 5 ms timing simulation instead of only 2 ms. it allows comparison of waveforms before and after design changes. warp enterprise ? warp enterprise provides even more features. it provides un- limited timing simulation and source-level behavioral simula- tion as well as a debugger. it has the ability to generate graph- ical hdl blocks from hdl text. it can even generate testbenches. warp is available for pc and unix platforms. some features are not available in the unix version. for further information see the warp for pc , warp for unix, warp professional and warp enterprise data sheets on cypress ? s web site (www.cypress.com). third-party software although warp is a complete cpld development tool on its own, it interfaces with nearly every third party eda tool. all major third-party software vendors provide support for the ultra37000 family of devices. refer to the third-party software data sheet or contact your local sales office for a list of current- ly supported third-party vendors. programming there are four programming options available for ultra37000 devices. the first method is to use a pc with the 37000 ultraisr programming cable and software. with this method, the isr pins of the ultra37000 devices are routed to a connec- tor at the edge of the printed circuit board. the 37000 ultraisr programming cable is then connected between the parallel port of the pc and this connector. a simple configuration file instructs the isr software of the programming operations to be performed on each of the ultra37000 devices in the system. the isr software then automatically completes all of the nec- essary data manipulations required to accomplish the pro- gramming, reading, verifying, and other isr functions. for more information on the cypress isr interface, see the isr programming kit data sheet (cy3700i). the second method for programming ultra37000 devices is on automatic test equipment (ate). this is accomplished through a file created by the isr software. check the cypress website for the latest isr software download information. the third programming option for ultra37000 devices is to uti- lize the embedded controller or processor that already exists in the system. the ultra37000 isr software assists in this method by converting the device jedec maps into the isr serial stream that contains the isr instruction information and the addresses and data of locations to be programmed. the embedded controller then simply directs this isr stream to the chain of ultra37000 devices to complete the desired reconfig- uring or diagnostic operations. contact your local sales office for information on availability of this option. the fourth method for programming ultra37000 devices is to use the same programmer that is currently being used to pro- gram f lash 370i devices. for all pinout, electrical, and timing requirements, refer to de- vice data sheets. for isr cable and software specifications, refer to the ultraisr kit data sheet (cy3700i). third-party programmers as with development software, cypress support is available on a wide variety of third-party programmers. all major third-party programmers (including bp micro, data i/o, and sms) support the ultra37000 family. figure 6. jtag interface instruction register boundary scan idcode usercode isr prog. bypass reg. data registers jtag tap controller tdo tdi tms tck ultra37000 ? cpld family document #: 38-03007 rev. ** page 9 of 67 logic block diagrams cy37032 / cy37032v logic block b logic block a 36 16 36 16 input clock/ input 16 i/os 16 i/os i/o 0 ? i/o 15 i/o 16 ? i/o 31 4 4 4 16 16 tdi tck tms tdo jtag tap controller 1 pim jtag en logic block d logic block c logic block a logic block b 36 16 36 16 36 16 36 16 input clock/ input 16 i/os 16 i/os 16 i/os 16 i/os i/o 0 -i/o 15 i/o 16 -i/o 31 i/o 48 -i/o 63 i/o 32 -i/o 47 4 4 4 32 32 tdi tck tms tdo jtag tap controller 1 pim cy37064 / cy37064v (100-lead tqfp) ultra37000 ? cpld family document #: 38-03007 rev. ** page 10 of 67 logic block diagrams (continued) tdi tck tms tdo jtag tap controller cy37128 / cy37128v (160-lead tqfp) pim input macrocell clock inputs 4 4 36 16 16 36 logic block 36 16 16 36 16 i/os 36 36 36 16 16 36 16 16 64 64 4 1 input/clock macrocells i/o 0 ? i/o 15 a inputs logic block c logic block b logic block d logic block h logic block g logic block f logic block e i/o 16 ? i/o 31 i/o 32 ? i/o 47 i/o 28 ? i/o 63 i/o 112 ? i/o 127 i/o 96 ? i/o 111 i/o 80 ? i/o 95 i/o 64 ? i/o 79 16 i/os 16 i/os 16 i/os 16 i/os 16 i/os 16 i/os 16 i/os jtag en logic block h logic block l logic block i logic block j logic block k logic block a logic block b logic block c logic block d logic block e logic block g logic block f 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 pim input clock/ input 10 i/os 10 i/os 10 i/os 10 i/os 10 i/os 10 i/os 10 i/os 10 i/os 10 i/os 10 i/os 10 i/os 10 i/os i/o 0 ? i/o 9 i/o 10 ? i/o 19 i/o 20 ? i/o 29 i/o 30 ? i/o 39 i/o 40 ? i/o 49 i/o 50 ? i/o 59 i/o 110 ? i/o 119 i/o 100 ? i/o 109 i/o 90 ? i/o 99 i/o 80 ? i/o 89 i/o 70 ? i/o 79 i/o 60 ? i/o 69 4 4 4 60 60 tdi tck tms tdo jtag tap controller 1 cy37192 / cy37192v (160-lead tqfp) ultra37000 ? cpld family document #: 38-03007 rev. ** page 11 of 67 logic block diagrams (continued) cy37256 / cy37256v (256-lead bga) logic block g logic block h logic block i logic block j logic block l logic block p logic block m logic block n logic block o logic block a logic block b logic block c logic block d logic block e logic block k logic block f 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 pim input clock/ input 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os i/o 0 ? i/o 11 i/o 12 ? i/o 23 i/o 24 ? i/o 35 i/o 36 ? i/o 47 i/o 48 ? i/o 59 i/o 60 ? i/o 71 i/o 72 ? i/o 83 i/o 84 ? i/o 95 i/o 180 ? i/o 191 i/o 168 ? i/o 179 i/o 156 ? i/o 167 i/o 144 ? i/o 155 i/o 132 ? i/o 143 i/o 120 ? i/o 131 i/o 108 ? i/o 119 i/o 96 ? i/o 107 4 4 4 96 96 tdi tck tms tdo jtag tap controller 1 ultra37000 ? cpld family document #: 38-03007 rev. ** page 12 of 67 logic block diagrams (continued) cy37384 / cy37384v (256-lead bga) logic block ah logic block ai logic block bd logic block be logic block bg logic block bl logic block bi logic block bj logic block bk logic block aa logic block ab logic block ac logic block ad logic block af logic block bf logic block ag 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 pim input clock/ input 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os i/o 0 ? i/o 11 i/o 12 ? i/o 23 i/o 24 ? i/o 35 i/o 48 ? i/o 59 i/o 60 ? i/o 71 i/o 72 ? i/o 83 i/o 168 ? i/o 191 i/o 156 ? i/o 179 i/o 144 ? i/o 167 i/o 120 ? i/o 143 i/o 108 ? i/o 131 4 4 4 96 96 tdi tck tms tdo jtag tap controller 1 logic block aj logic block bc 16 16 12 i/os i/o 96 ? i/o 119 logic block ak logic block bb 16 16 12 i/os i/o 84 ? i/o 95 logic block al logic block ba 16 16 12 i/os i/o 96 ? i/o 107 logic block ae logic block bh 16 16 12 i/os 12 i/os i/o 36 ? i/o 47 i/o 132 ? i/o 155 36 36 36 36 36 36 36 36 ultra37000 ? cpld family document #: 38-03007 rev. ** page 13 of 67 logic block diagrams (continued) cy37512 / cy37512v (352-lead bga) logic block ag logic block ah logic block bi logic block bj logic block bl logic block bp logic block bm logic block bn logic block bo logic block aa logic block ab logic block ac logic block ad logic block ae logic block bk logic block af 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 36 36 16 36 16 36 16 36 16 36 16 36 16 36 16 input clock/ input 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os 12 i/os i/o 0 ? i/o 11 i/o 12 ? i/o 23 i/o 24 ? i/o 35 i/o 36 ? i/o 47 i/o 48 ? i/o 59 i/o 60 ? i/o 71 i/o 72 ? i/o 83 i/o 84 ? i/o 95 i/o 252 ? i/o 263 i/o 240 ? i/o 251 i/o 228 ? i/o 239 i/o 216 ? i/o 227 i/o 204 ? i/o 215 4 4 4 tdi tck tms tdo jtag tap controller 1 pim 16 36 36 16 logic block ai logic block bh 12 i/os i/o 96 ? i/o 107 16 36 36 16 logic block aj logic block bg 12 i/os 12 i/os i/o 108 ? i/o 119 i/o 192 ? i/o 203 16 36 36 16 logic block ak logic block bf 12 i/os i/o 120 ? i/o 131 16 36 36 16 logic block al logic block be 12 i/os i/o 180 ? i/o 191 16 36 36 16 logic block am logic block bd 12 i/os i/o 168 ? i/o 179 16 36 36 16 logic block an logic block bc 12 i/os i/o 156 ? i/o 167 16 36 36 16 logic block ao logic block bb 12 i/os i/o 144 ? i/o 155 16 36 36 16 logic block ap logic block ba 12 i/os i/o 132 ? i/o 143 16 132 132 16 ultra37000 ? cpld family document #: 38-03007 rev. ** page 14 of 67 5.0v device characteristics maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage to ground potential ............... ? 0.5v to +7.0v dc voltage applied to outputs in high z state................................................ ? 0.5v to +7.0v dc input voltage ............................................ ? 0.5v to +7.0v dc program voltage ............................................ 4.5 to 5.5v current into outputs .................................................... 16 ma static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma operating range [2] range ambient temperature [2] junction temperature output condition v cc v cco commercial 0 c to +70 c 0 c to +90 c 5v 5v 0.25v 5v 0.25v 3.3v 5v 0.25v 3.3v 0.3v industrial ? 40 c to +85 c ? 40 c to +105 c 5v 5v 0.5v 5v 0.5v 3.3v 5v 0.5v 3.3v 0.3v military [3] ? 55 c to +125 c ? 55 c to +130 c 5v 5v 0.5v 5v 0.5v 3.3v 5v 0.5v 3.3v 0.3v notes: 2. normal programming conditions apply across ambient temperature range for specified programming methods. for more information on programming the ultra37000 family devices, please refer to the application note titled ? an introduction to in system reprogramming with the ultra37000. ? 3. t a is the ? instant on ? case temperature. ultra37000 ? cpld family document #: 38-03007 rev. ** page 15 of 67 5.0v device electrical characteristics over the operating range parameter description test conditions min. typ. max. unit v oh output high voltage v cc = min. i oh = ? 3.2 ma (com ? l/ind) [4] 2.4 v i oh = ? 2.0 ma (mil) [4] 2.4 v v ohz output high voltage with output disabled [5] v cc = max. i oh = 0 a (com ? l) [6] 4.2 v i oh = 0 a (ind/mil) [6] 4.5 v i oh = ? 100 a (com ? l) [6] 3.6 v i oh = ? 150 a (ind/mil) [6] 3.6 v v ol output low voltage v cc = min. i ol = 16 ma (com ? l/ind) [4] 0.5 v i ol = 12 ma (mil) [4] 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs [7] 2.0 v ccmax v v il input low voltage guaranteed input logical low voltage for all inputs [7] ? 0.5 0.8 v i ix input load current v i = gnd or v cc , bus-hold disabled ? 10 10 a i oz output leakage current v o = gnd or v cc , output disabled, bus-hold disabled ? 50 50 a i os output short circuit current [8, 5] v cc = max., v out = 0.5v ? 30 ? 160 ma i bhl input bus-hold low sustaining current v cc = min., v il = 0.8v +75 a i bhh input bus-hold high sustaining current v cc = min., v ih = 2.0v ? 75 a i bhlo input bus-hold low overdrive current v cc = max. +500 a i bhho input bus-hold high overdrive current v cc = max. ? 500 a inductance [5] parameter description test conditions 44- lead tqfp 44- lead plcc 44- lead clcc 84- lead plcc 84- lead clcc 100- lead tqfp 160- lead tqfp 208- lead pqfp unit l maximum pin inductance v in = 5.0v at f = 1 mhz 2 5 2 8 5 8 9 11 nh capacitance [5] parameter description test conditions max. unit c i/o input/output capacitance v in = 5.0v at f = 1 mhz at t a = 25 c 10 pf c clk clock signal capacitance v in = 5.0v at f = 1 mhz at t a = 25 c 12 pf c dp dual function pins [9] v in = 5.0v at f = 1 mhz at t a = 25 c 16 pf endurance characteristics [5] parameter description test conditions min. typ. unit n minimum reprogramming cycles normal programming conditions [2] 1,000 10,000 cycles notes: 4. i oh = ? 2 ma, i ol = 2 ma for tdo. 5. tested initially and after any design or process changes that may affect these parameters. 6. when the i/o is output disabled, the bus-hold circuit can weakly pull the i/o to above 3.6v if no leakage current is allowed. note that all i/os are output disabled during isr programming. refer to the application note ? understanding bus-hold ? for additional information. 7. these are absolute values with respect to device ground. all overshoots due to system or tester noise are included. 8. not more than one output should be tested at a time. duration of the short circuit should not exceed 1 second. v out = 0.5v has been chosen to avoid test problems caused by tester ground degradation. 9. dual pins are i/o with jtag pins. ultra37000 ? cpld family document #: 38-03007 rev. ** page 16 of 67 3.3v device characteristics maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage to ground potential ............... ? 0.5v to +4.6v dc voltage applied to outputs in high z state................................................ ? 0.5v to +7.0v dc input voltage ............................................ ? 0.5v to +7.0v dc program voltage ............................................ 3.0 to 3.6v current into outputs ...................................................... 8 ma static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma operating range [2] range ambient temperature [2] junction temperature v cc commercial 0 c to +70 c 0 c to +90 c 3.3v 0.3v industrial ? 40 c to +85 c ? 40 c to +105 c3.3v 0.3v military [3] ? 55 c to +125 c ? 55 c to +130 c3.3v 0.3v 3.3v device electrical characteristics over the operating range parameter description test conditions min. max. unit v oh output high voltage v cc = min. i oh = ? 4 ma (com ? l) [4] 2.4 v i oh = ? 3 ma (mil) [4] v ol output low voltage v cc = min. i ol = 8 ma (com ? l) [4] 0.5 v i ol = 6 ma (mil) [4] v ih input high voltage guaranteed input logical high voltage for all inputs [7] 2.0 5.5 v v il input low voltage guaranteed input logical low voltage for all inputs [7] ? 0.5 0.8 v i ix input load current v i = gnd or v cc , bus-hold disabled ? 10 10 a i oz output leakage current v o = gnd or v cc , output disabled, bus-hold disabled ? 50 50 a i os output short circuit current [8, 5] v cc = max., v out = 0.5v ? 30 ? 160 ma i bhl input bus-hold low sustaining current v cc = min., v il = 0.8v +75 a i bhh input bus-hold high sustaining current v cc = min., v ih = 2.0v ? 75 a i bhlo input bus-hold low overdrive current v cc = max. +500 a i bhho input bus-hold high overdrive current v cc = max. ? 500 a inductance [5] parameter description test conditions 44- lead tqfp 44- lead plcc 44- lead clcc 84- lead plcc 84- lead clcc 100- lead tqfp 160- lead tqfp 208- lead pqfp unit l maximum pin inductance v in = 3.3v at f = 1 mhz 2 5 2 8 5 8 9 11 nh ultra37000 ? cpld family document #: 38-03007 rev. ** page 17 of 67 ac characteristics. capacitance [5] parameter description test conditions max. unit c i/o input/output capacitance v in = 3.3v at f = 1 mhz at t a = 25 c 8 pf c clk clock signal capacitance v in = 3.3v at f = 1 mhz at t a = 25 c 12 pf c dp dual functional pins [9] v in = 3.3v at f = 1 mhz at t a = 25 c 16 pf endurance characteristics [5] parameter description test conditions min. typ. unit n minimum reprogramming cycles normal programming conditions [2] 1,000 10,000 cycles 5.0v ac test loads and waveforms 3.3v ac test loads and waveforms 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 35 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) < 2 ns output 238 ? (com ? l) 319 ? (mil) 170 ? (com ? l) 236 ? (mil) 99 ? (com ? l) 136 ? (mil) equivalent to: th venin equivalent 2.08v (com'l) 2.13v (mil) 238 ? (com'l) 319 ? (mil) 170 ? (com'l) 236 ? (mil) < 2 ns (c) 5 or 35 pf 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 35 pf including jig and scope 3.3v output 5 pf including jig and scope (a) (b) < 2 ns output 295 ? (com ? l) 393 ? (mil) 340 ? (com ? l) 453 ? (mil) equivalent to: th venin equivalent 1.77v (com'l) 1.77v (mil) 295 ? (com'l) 393 ? (mil) 340 ? (com'l) 453 ? (mil) < 2 ns (c) 270 ? (mil) 158 ? (com ? l) 5 or 35 pf ultra37000 ? cpld family document #: 38-03007 rev. ** page 18 of 67 note: 10. t er measured with 5-pf ac test load and t ea measured with 35-pf ac test load. parameter [10] v x output waveform ? measurement level t er( ? ) 1.5v t er(+) 2.6v t ea(+) 1.5v t ea( ? ) v the (d) test waveforms v oh v x 0.5v v ol v x 0.5v v x v oh 0.5v v x v ol 0.5v ultra37000 ? cpld family document #: 38-03007 rev. ** page 19 of 67 switching characteristics over the operating range [11] parameter description unit combinatorial mode parameters t pd [12, 13, 14] input to combinatorial output ns t pdl [12, 13, 14] input to output through transparent input or output latch ns t pdll [12, 13, 14] input to output through transparent input and output latches ns t ea [12, 13, 14] input to output enable ns t er [10, 12] input to output disable ns input register parameters t wl clock or latch enable input low time [8] ns t wh clock or latch enable input high time [8] ns t is input register or latch set-up time ns t ih input register or latch hold time ns t ico [12, 13, 14] input register clock or latch enable to combinatorial output ns t icol [12, 13, 14] input register clock or latch enable to output through transparent output latch ns synchronous clocking parameters t co [13, 14] synchronous clock (clk 0 , clk 1 , clk 2 , or clk 3 ) or latch enable to output ns t s [12] set-up time from input to sync. clk (clk 0 , clk 1 , clk 2 , or clk 3 ) or latch enable ns t h register or latch data hold time ns t co2 [12, 13, 14] output synchronous clock (clk 0 , clk 1 , clk 2 , or clk 3 ) or latch enable to combinatorial output delay (through logic array) ns t scs [12] output synchronous clock (clk 0 , clk 1 , clk 2 , or clk 3 ) or latch enable to output synchronous clock (clk 0 , clk 1 , clk 2 , or clk 3 ) or latch enable (through logic array) ns t sl [12] set-up time from input through transparent latch to output register synchronous clock (clk 0 clk 1 , clk 2 , or clk 3 ) or latch enable ns t hl hold time for input through transparent latch from output register synchronous clock (clk 0 , clk 1 , clk 2 , or clk 3 ) or latch enable ns product term clocking parameters t copt [12, 13, 14] product term clock or latch enable (ptclk) to output ns t spt set-up time from input to product term clock or latch enable (ptclk) ns t hpt register or latch data hold time ns t ispt [12] set-up time for buried register used as an input register from input to product term clock or latch enable (ptclk) ns t ihpt buried register used as an input register or latch data hold time ns t co2pt [12, 13, 14] product term clock or latch enable (ptclk) to output delay (through logic array) ns pipelined mode parameters t ics [12] input register synchronous clock (clk 0 , clk 1 , clk 2 , or clk 3 ) to output register synchronous clock (clk 0 , clk 1 , clk 2 , or clk 3 ) ns notes: 11. all ac parameters are measured with two outputs switching and 35-pf ac test load. 12. logic blocks operating in low-power mode, add t lp to this spec. 13. outputs using slow output slew rate, add t slew to this spec. 14. when v cco = 3.3v, add t 3.3io to this spec. ultra37000 ? cpld family document #: 38-03007 rev. ** page 20 of 67 operating frequency parameters f max1 maximum frequency with internal feedback (lesser of 1/t scs , 1/(t s + t h ), or 1/t co ) [5] mhz f max2 maximum frequency data path in output registered/latched mode (lesser of 1/(t wl + t wh ), 1/(t s + t h ), or 1/t co ) [5] mhz f max3 maximum frequency with external feedback (lesser of 1/(t co + t s ) or 1/(t wl + t wh ) [5] mhz f max4 maximum frequency in pipelined mode (lesser of 1/(t co + t is ), 1/t ics , 1/(t wl + t wh ), 1/(t is + t ih ), or 1/t scs ) [5] mhz reset/preset parameters t rw asynchronous reset width [5] ns t rr [12] asynchronous reset recovery time [5] ns t ro [12, 13, 14] asynchronous reset to output ns t pw asynchronous preset width [5] ns t pr [12] asynchronous preset recovery time [5] ns t po [12, 13, 14] asynchronous preset to output ns user option parameters t lp low power adder ns t slew slow output slew rate adder ns t 3.3io 3.3v i/o mode timing adder [5] ns jtag timing parameters t s jtag set-up time from tdi and tms to tck [5] ns t h jtag hold time on tdi and tms [5] ns t co jtag falling edge of tck to tdo [5] ns f jtag maximum jtag tap controller frequency [5] ns switching characteristics over the operating range [11] (continued) parameter description unit ultra37000 ? cpld family document #: 38-03007 rev. ** page 21 of 67 switching characteristics over the operating range [11] 200 mhz 167 mhz 154 mhz 143 mhz 125 mhz 100 mhz 83 mhz 66 mhz parameter min. max. min. max. min. max. min. max. min. max. min. max. min. max. min. max. unit combinatorial mode parameters t pd [12, 13, 14] 6 6.5 7.5 8.5 10 12 15 20 ns t pdl [12, 13, 14] 11 12.5 14.5 16 16.5 17 19 22 ns t pdll [12, 13, 14] 12 13.5 15.5 17 17.5 18 20 24 ns t ea [12, 13, 14] 8 8.5 11 13 14 16 19 24 ns t er [10, 12] 8 8.5 11 13 14 16 19 24 ns input register parameters t wl 2.5 2.5 2.5 2.5 3 3 4 5 ns t wh 2.5 2.5 2.5 2.5 3 3 4 5 ns t is 2 222 2 2.5 3 4ns t ih 2 222 2 2.5 3 4ns t ico [12, 13, 14] 11 11 11 12.5 12.5 16 19 24 ns t icol [12, 13, 14] 12 12 12 14 16 18 21 26 ns synchronous clocking parameters t co [13, 14] 4 4 4.5 6 6.5 [15] 6.5 [16] 8 [17] 10 ns t s [12] 44555.5 [15] 6 [16] 8 [17] 10 ns t h 0000 0 0 0 0ns t co2 [12, 13, 14] 9.5 10 11 12 14 16 19 24 ns t scs [12] 5 66.57 8 [15] 10 12 15 ns t sl [12] 7.5 7.5 8.5 9 10 12 15 15 ns t hl 0 000 0 0 0 0ns product term clocking parameters t copt [12, 13, 14] 7101013 13 13 1520ns t spt 2.5 2.5 2.5 3 5 5.5 6 7 ns t hpt 2.5 2.5 2.5 3 5 5.5 6 7 ns t ispt [12] 000 0 00 00ns t ihpt 6 6.5 6.5 7.5 9 11 14 19 ns t co2pt [12, 13, 14] 12 14 15 19 19 21 24 30 ns pipelined mode parameters t ics [12] 56678 [15] 10 12 15 ns operating frequency parameters f max1 200 167 154 143 125 [15] 100 83 66 mhz f max2 200 200 200 167 154 153 [16] 125 [17] 100 mhz f max3 125 125 105 91 83 80 [16] 62.5 50 mhz f max4 167 167 154 125 118 100 83 66 mhz notes: 15. the following values correspond to the cy37512 and cy37384 devices: t co = 5 ns, t s = 6.5 ns, t scs = 8.5 ns, t ics = 8.5 ns, f max1 = 118 mhz. 16. the following values correspond to the cy37192v and cy37256v devices: t co = 6 ns, t s = 7 ns, f max2 = 143 mhz, f max3 = 77 mhz, and f max4 = 100 mhz; and for the cy37512 devices: t s = 7 ns. 17. the following values correspond to the cy37512v and cy37384v devices: t co = 6.5 ns, t s = 9.5 ns, and f max2 = 105 mhz. ultra37000 ? cpld family document #: 38-03007 rev. ** page 22 of 67 reset/preset parameters t rw 8 888 10 12 15 20ns t rr [12] 10 10 10 10 12 14 17 22 ns t ro [12, 13, 14] 12 13 13 14 15 18 21 26 ns t pw 8 888 10 12 15 20ns t pr [12] 10 10 10 10 12 14 17 22 ns t po [12, 13, 14] 12 13 13 14 15 18 21 26 ns user option parameters t lp 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t slew 3333 3 3 33ns t 3.3io [18] 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 ns jtag timing parameters t s jtag 0 00 0 00 00ns t h jtag 20 20 20 20 20 20 20 20 ns t co jtag 20 20 20 20 20 20 20 20 ns f jtag 20 20 20 20 20 20 20 20 mhz note: 18. only applicable to the 5v devices. switching characteristics over the operating range [11] (continued) 200 mhz 167 mhz 154 mhz 143 mhz 125 mhz 100 mhz 83 mhz 66 mhz parameter min. max. min. max. min. max. min. max. min. max. min. max. min. max. min. max. unit ultra37000 ? cpld family document #: 38-03007 rev. ** page 23 of 67 switching waveforms t pd input combinatorial output combinatorial output registered output with synchronous clocking t s input synchronous t co registered output t h synchronous t wl t wh t co2 registered output clock clock registered output with product term clocking t spt input product term t copt registered output t hpt clock input going through the array ultra37000 ? cpld family document #: 38-03007 rev. ** page 24 of 67 switching waveforms (continued) registered output with product term clocking t ispt input product term t co2pt registered output t ihpt clock input coming from adjacent buried register latched output t sl input latch enable t co latched output t hl t pdl registered input t is registered input input register clock t ico combinatorial output t ih clock t wl t wh ultra37000 ? cpld family document #: 38-03007 rev. ** page 25 of 67 switching waveforms (continued) clock to clock input register clock output register clock t scs t ics latched input t is latched input latch enable t ico combinatorial output t ih t pdl t wl t wh latch enable latched input and output t ics latched input output latch enable latched output t pdll latch enable t wl t wh t icol input latch enable t sl t hl ultra37000 ? cpld family document #: 38-03007 rev. ** page 26 of 67 switching waveforms (continued) asynchronous reset input t ro registered output clock t rr t rw asynchronous preset input t po registered output clock t pr t pw output enable/disable input t er outputs t ea ultra37000 ? cpld family document #: 38-03007 rev. ** page 27 of 67 power consumption typical 5.0v power consumption cy37032 cy37064 0 10 20 30 40 50 60 0 50 100 150 200 250 frequency (mhz) icc (ma) high speed low power the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 5.0v, t a = room temperature the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 5.0v, t a = room temperature 0 10 20 30 40 50 60 70 80 90 0 20 40 60 80 100 120 140 160 180 frequency (mhz) icc (ma) low power high speed ultra37000 ? cpld family document #: 38-03007 rev. ** page 28 of 67 cy37128 cy37192 typical 5.0v power consumption (continued) 0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160 180 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 5.0v, t a = room temperature 0 50 100 150 200 250 300 0 20 40 60 80 100 120 140 160 180 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 5.0v, t a = room temperature ultra37000 ? cpld family document #: 38-03007 rev. ** page 29 of 67 cy37256 cy37384 typical 5.0v power consumption (continued) 0 50 100 150 200 250 300 0 20 40 60 80 100 120 140 160 180 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 5.0v, t a = room temperature 0 50 100 150 200 250 300 350 400 450 500 0 20406080100120140160 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 5.0v, t a = room temperature ultra37000 ? cpld family document #: 38-03007 rev. ** page 30 of 67 cy37512 typical 5.0v power consumption (continued) 0 100 200 300 400 500 600 0 20 40 60 80 100 120 140 160 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 5.0v, t a = room temperature typical 3.3v power consumption cy37032v 0 5 10 15 20 25 30 0 20 40 60 80 100 120 140 160 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 3.3v, t a = room temperature ultra37000 ? cpld family document #: 38-03007 rev. ** page 31 of 67 cy37064v cy37128v typical 3.3v power consumption (continued) 0 5 10 15 20 25 30 35 40 45 0 20406080100120140 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 3.3v, t a = room temperature 0 10 20 30 40 50 60 70 80 0 20 40 60 80 100 120 140 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 3.3v, t a = room temperature ultra37000 ? cpld family document #: 38-03007 rev. ** page 32 of 67 cy37192v cy37256v typical 3.3v power consumption (continued) 0 20 40 60 80 100 120 0 20 40 60 80 100 120 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 3.3v, t a = room temperature 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 3.3v, t a = room temperature ultra37000 ? cpld family document #: 38-03007 rev. ** page 33 of 67 cy37384v cy37512v typical 3.3v power consumption (continued) 0 20 40 60 80 100 120 140 160 180 200 0 102030405060708090 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 3.3v, t a = room temperature 0 50 100 150 200 250 0 102030405060708090 frequency (mhz) icc (ma) low power high speed the typical pattern is a 16-bit up counter, per logic block, with outputs disabled. v cc = 3.3v, t a = room temperature ultra37000 ? cpld family document #: 38-03007 rev. ** page 34 of 67 pin configurations [19] note: 19. for 3.3v versions (ultra37000v), v cco = v cc . 44-pin tqfp (a44) top view i/o 2 gnd v cco i/o 3 i/o 4 i/o 1 i/o 0 i/o 29 i/o 30 i/o 31 i/o 28 i/o 27 /tdi i/o 26 i/o 25 i/o 24 clk 1 /i 4 gnd i 3 clk 3 /i 2 i/o 23 i/o 22 i/o 21 gnd i/o 20 v cc i/o 18 i/o 17 i/o 16 i/o 15 i/o 14 i/o 12 i/o 5 /tck i/o 6 i/o 7 clk 2 /i 0 gnd clk 0 /i 1 i/o 8 i/o 9 i/o 10 i/o 11 8 9 7 10 11 3 4 2 5 6 1 18 19 20 22 21 13 14 15 17 16 12 31 30 29 32 33 26 25 24 27 28 23 44 43 42 40 41 39 38 37 35 36 34 i/o 13 /tms i/o 19 /tdo jtag en 44-pin plcc (j67) / clcc (y67) top view i/o 27 /tdi i/o 26 i/o 25 i/o 24 clk 1 /i 4 gnd i 3 clk 3 /i 2 i/o 23 i/o 22 i/o 21 i/o 5 /tck i/o 6 i/o 7 clk 2 /i 0 jtag en gnd clk 0 /i 1 i/o 8 i/o 9 i/o 10 i/o 11 gnd i/o 20 i/o 2 gnd v cco v cc i/o 3 i/o 4 i/o 1 i/o 0 i/o 29 i/o 30 i/o 31 i/o 28 i/o 19 i/o 18 i/o 17 i/o 16 i/o 15 i/o 14 i/o 13 i/o 12 65 3 4 2 8 9 7 10 11 44 18 15 16 14 13 12 17 19 20 22 21 23 24 27 26 28 25 31 30 29 32 33 34 39 37 38 36 35 43 42 40 41 /tms /tdo 1 ultra37000 ? cpld family document #: 38-03007 rev. ** page 35 of 67 pin configurations [19] (continued) 48-ball fine-pitch bga (ba50) top view 12345678 ai/o 5 tck v cc i/o 3 i/o 1 i/o 31 i/o 30 v cc i/o 27 tdi bv cc i/o 4 i/o 2 i/o 0 i/o 29 i/o 28 i/o 26 clk 1 / i 4 cclk 2 / i 0 i/o 7 i/o 6 gnd gnd i/o 25 i/o 24 i 3 djtag en i/o 8 i/o 9 gnd gnd i/o 22 i/o 23 clk 3 / i 2 eclk 0 / i 1 i/o 12 i/o 11 i/o 10 i/o 16 i/o 20 i/o 21 v cc f i/o 13 tms v cc i/o 14 i/o 15 i/o 17 i/o 18 v cc i/o 19 tdo ultra37000 ? cpld family document #: 38-03007 rev. ** page 36 of 67 note: 20. this pin is a n/c, but cypress recommends that you connect it to v cc to ensure future compatibility. pin configurations [19] (continued) i/o i/o 14 i/o 15 i/o 48 top view 84-lead plcc (j83) / clcc (y84) 98 6 7 5 13 14 12 11 49 48 58 59 60 23 24 26 25 27 15 16 47 46 43 28 33 20 21 19 18 17 22 34 37 36 38 42 41 43 40 66 65 63 64 62 61 67 68 69 74 72 73 71 70 84 81 82 80 79 gnd i/o gnd i/o i/o i/o i/o i/o i/o i/o gnd i/o 55 i/o 54 /tdi i/o 53 i/o 52 i/o 51 gnd i/o 49 clk 3 /i 4 v cco clk 2 /i 3 i/o 45 i/o 44 gnd i/o i/o 8 i/o 9 i/o 10 /tck i/o 11 i/o 12 i/o 13 clk 0 /i 0 v cco clk 1 /i 1 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 53 52 51 50 30 29 31 32 i/o i/o i/o i/o 54 55 56 57 i/o 43 i/o 42 i/o 41 i/o 40 77 78 76 75 i/o 21 i/o 22 i/o 23 gnd i/o i/o 50 i/o 47 i/o 46 gnd 24 i/o 25 /tms i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 v cco v cc i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 gnd i 2 7 6 5 4 3 2 1 v cco i/o 0 v cc 63 i/o 62 61 60 59 58 57 56 jtag en i/o 26 /tdo 10 35 39 44 45 83 2 1 [ 20 ] ultra37000 ? cpld family document #: 38-03007 rev. ** page 37 of 67 pin configurations [19] (continued) top view 100-lead tqfp (a100) 100 97 98 96 2 3 1 42 41 59 60 61 12 13 15 14 16 4 5 40 39 95 94 17 26 9 10 8 7 6 11 27 28 30 29 31 32 35 34 36 38 33 67 66 64 65 63 62 68 69 70 75 73 74 72 71 89 88 86 87 85 93 92 84 tdi nc v cco i/o 55 i/o 54 i/o 53 i/o 52 clk 3 /i 4 i/o 50 i/o 48 gnd nc i / o 47 i/o 46 i/o 49 gnd tms tck gnd i/o 8 i/o 9 i/o 10 i/o 11 i/o 15 v cco gnd clk 1 /i 1 i/o 16 i/o 17 clk 0 /i 0 90 91 i/o 51 v cco clk 2 /i 3 i/o 14 n/c i/o 12 i/o 13 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 gnd nc gnd nc i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 v cco nc 18 19 20 21 22 23 24 25 83 82 81 80 79 78 77 76 58 57 56 55 54 53 52 51 43 44 45 46 48 49 50 gnd i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 v cco v cc i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i 2 nc v cco tdo i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o 7 6 5 4 3 2 1 v cco i/o 0 v cc nc 63 i/o 62 61 60 59 58 57 56 v cco n/c 99 37 47 [ 20 ] ultra37000 ? cpld family document #: 38-03007 rev. ** page 38 of 67 pin configurations [19] (continued) 100-ball fine-pitch bga (bb100) for cy37064v top view 100-ball fine-pitch bga (bb100) for cy37128v top view 12345678910 a nc nc i/o 7 i/o 5 i/o 2 i/o 62 i/o 60 i/o 58 i/o 57 i/o 56 b i/o 9 i/o 8 i/o 6 i/o 4 i/o 1 i/o 63 v cc i/o 59 i/o 55 nc c i/o 10 tck v cc i/o 3 nc nc i/o 61 v cc tdi i/o 54 d i/o 11 nc i/o 12 i/o 13 i/o 0 nc i/o 51 i/o 52 clk 3 / i 4 i/o 53 e i/o 14 clk 0 / i 0 i/o 15 nc gnd gnd i/o 48 i/o 49 clk 2 / i 3 i/o 50 f i/o 17 nc nc i/o 16 gnd gnd nc nc i 2 i/o 47 g i/o 22 clk 1 / i 1 i/o 21 i/o 19 i/o 18 i/o 46 i/o 45 i/o 44 nc i/o 43 h i/o 23 tms v cc i/o 20 nc i/o 32 i/o 42 v cc tdo i/o 41 j nc i/o 26 i/o 28 nc i/o 31 i/o 33 i/o 35 i/o 37 i/o 39 i/o 40 k i/o 24 i/o 25 i/o 27 i/o 29 i/o 30 i/o 34 i/o 36 i/o 38 nc nc 12345678910 a nc i/o 9 i/o 8 i/o 6 i/o 3 i/o 76 i/o 74 i/o 72 i/o 71 i/o 70 b i/o 11 i/o 10 i/o 7 i/o 5 i/o 2 i/o 77 v cc i/o 73 i/o 68 i/o 69 c i/o 12 i/o 13 tck v cc i/o 4 i/o 1 i/o 78 i/o 75 v cc i/o 67 tdi i/o 66 d i/o 14 v cc i/o 15 i/o 16 i/o 0 i/o 79 i/o 63 i/o 64 clk 3 / i 4 i/o 65 e i/o 17 clk 0 / i 0 i/o 18 i/o 19 gnd gnd i/o 60 i/o 61 clk 2 / i 3 i/o 62 f i/o 22 jtag en i/o 21 i/o 20 gnd gnd i/o 59 i/o 58 i 2 i/o 57 g i/o 27 clk 1 / i 1 i/o 26 i/o 24 i/o 23 i/o 56 i/o 55 i/o 54 v cc i/o 53 h i/o 28 i/o 33 tms v cc i/o 25 i/o 39 i/o 40 i/o 52 v cc i/o 47 tdo i/o 51 j i/o 29 i/o 32 i/o 35 v cc i/o 38 i/o 41 i/o 43 i/o 45 i/o 48 i/o 50 k i/o 30 i/o 31 i/o 34 i/o 36 i/o 37 i/o 42 i/o 44 i/o 46 i/o 49 nc ultra37000 ? cpld family document #: 38-03007 rev. ** page 39 of 67 pin configurations [19] (continued) i/o 77 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 43 44 160 45 159 46 158 47 157 48 156 49 155 50 154 51 153 52 152 53 151 54 150 55 149 56 148 57 147 58 146 59 145 60 144 61 143 62 142 63 141 64 65 66 67 68 140 69 139 70 138 71 137 72 136 73 135 74 134 75 133 76 132 77 131 78 130 79 129 80 128 81 127 82 126 160-lead tqfp (a160) / cqfp (u162) 125 84 83 42 gnd i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 /tck i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 gnd clk 0 /i 0 v cco gnd clk 1 /i 1 gnd gnd gnd gnd gnd v cco i/o 48 i/o 49 i/o 50 i/o 51 i/o 53 i/o 54 i/o 55 i/o 56 i/o 57 i/o 58 i/o 59 i/o 60 i/o 61 i/o 62 i/o 63 i 2 v cco v cc i/o 64 i/o 65 i/o 66 i/o 67 i/o 68 i/o 69 i/o 70 i/o 71 i/o 72 i/o 73 i/o 74 i/o 75 i/o 78 i/o 79 v cco gnd i/o 80 i/o 81 i/o 82 i/o 83 i/o 84 i/o 85 i/o 86 i/o 87 gnd i/o 88 i/o 89 i/o 90 i/o 91 i/o 92 i/o 93 i/o 94 i/o 95 i/o 96 i/o 97 i/o 98 i/o 99 i/o 100 i/o 101 i/o 102 i/o 103 gnd gnd clk 2 /i 3 v cco clk 3 /i 4 i/o 104 i/o 105 i/o 106 i/o 107 i/o 108 /tdi i/o 109 i/o 110 i/o 111 v cco gnd gnd v cc gnd i/o 112 gnd v cco v cco i/o 113 i/o 114 i/o 115 i/o 116 i/o 117 i/o 118 i/o 119 i/o 120 i/o 121 i/o 122 i/o 123 i/o 124 i/o 125 i/o 126 i/o 127 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 jtag en i/o 52 /tms i/o 76 /tdo 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 41 for cy37128(v) and cy37256(v) top view ultra37000 ? cpld family document #: 38-03007 rev. ** page 40 of 67 pin configurations [19] (continued) i/o 72 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 43 44 160 45 159 46 158 47 157 48 156 49 155 50 154 51 153 52 152 53 151 54 150 55 149 56 148 57 147 58 146 59 145 60 144 61 143 62 142 63 141 64 65 66 67 68 140 69 139 70 138 71 137 72 136 73 135 74 134 75 133 76 132 77 131 78 130 79 129 80 128 81 127 82 126 160-lead tqfp (a160) for cy37192(v) 125 84 83 42 gnd nc i/o 16 i/o 17 i/o 18 tck i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 gnd clk 0 /i 0 v cco gnd clk 1 /i 1 gnd gnd gnd gnd gnd v cco nc i/o 46 i/o 47 i/o 48 i/o 49 i/o 50 i/o 51 i/o 52 i/o 53 i/o 54 i/o 55 i/o 56 i/o 57 i/o 58 i/o 59 i 2 v cco v cc i/o 60 i/o 61 i/o 62 i/o 63 i/o 64 i/o 65 i/o 66 i/o 67 i/o 68 i/o 69 i/o 70 i/o 71 i/o 73 i/o 74 v cco gnd nc i/o 75 i/o 76 i/o 77 i/o 78 i/o 79 i/o 80 i/o 81 gnd i/o 82 i/o 83 i/o 84 i/o 85 i/o 86 i/o 87 i/o 88 i/o 89 i/o 90 i/o 91 i/o 92 i/o 93 i/o 94 i/o 95 i/o 96 i/o 97 gnd gnd clk 2 /i 3 v cco clk 3 /i 4 i/o 98 i/o 99 i/o 100 i/o 101 tdi i/o 102 i/o 103 i/o 104 v cco gnd gnd v cc gnd nc gnd v cco v cco i/o 105 i/o 106 i/o 107 i/o 108 i/o 109 i/o 110 i/o 111 i/o 112 i/o 113 i/o 114 i/o 115 i/o 116 i/o 117 i/o 118 i/o 119 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 nc tms tdo 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 41 top view ultra37000 ? cpld family document #: 38-03007 rev. ** page 41 of 67 pin configurations [19] (continued) i/o 152 i/o 154 i/o 153 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 41 42 43 44 45 46 47 48 49 50 51 52 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 208 167 166 165 164 163 162 161 160 159 158 157 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 53 92 93 94 95 96 97 98 99 100 101 102 103 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 155 115 114 113 112 111 110 109 108 107 106 105 156 104 207 208-lead pqfp (n208) / cqfp (u208) top view i/o 139 i/o 138 i/o 137 i/o 136 i/o 135 tdi i/o 134 i/o 133 i/o 132 i/o 131 i/o 130 gnd i/o 129 i/o 128 i/o 127 i/o 126 i/o 125 i/o 124 i/o 123 i/o 122 i/o 121 i/o 120 clk 3 /i 4 v cc gnd v cco gnd clk 2 /i 3 i/o 119 i/o 118 i/o 117 i/o 116 i/o 115 nc i/o 114 i/o 113 i/o 112 i/o 111 i/o 110 v cco gnd i/o 109 i/o 108 i/o 107 i/o 106 i/o 105 i/o 104 i/o 103 i/o 102 i/o 101 i/o 100 gnd i/o 61 i/o 62 i/o 63 i/o 64 tms i/o 65 i/o 66 i/o 67 i/o 68 i/o 69 gnd i/o 70 i/o 71 i/o 72 i/o 73 i/o 74 nc i/o 75 i/o 76 i/o 77 i/o 78 i/o 79 i 2 v cc0 gnd v cc i/o 80 i/o 81 i/o 82 i/o 83 i/o 84 i/o 85 i/o 86 i/o 87 i/o 88 i/o 89 gnd i/o 90 i/o 91 gnd i/o 92 i/o 93 i/o 94 gnd tdo i/o 95 i/o 96 i/o 97 i/o 98 i/o99 v cc0 i/o 60 i/o 21 i/o 22 i/o 23 i/o 24 tck i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 gnd i/o 30 i/o 31 i/o 32 i/o 33 i/o 34 nc i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 clk 0 /i 0 v cco gnd nc clk 1 /i 1 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 i/o 48 i/o 49 gnd i/o 50 i/o 20 i/o 51 i/o 52 i/o 53 i/o 54 nc i/o 55 i/o 56 i/o 57 i/o 58 i/o 59 v cc0 gnd v cc0 i/o 19 i/o 18 i/o 17 i/o 16 i/o 15 nc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 gnd i/o 9 i/o 8 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 v cc0 gnd v cc nc i/o 159 i/o 158 i/o 157 i/o 156 i/o 155 nc i/o 151 i/o 150 v cc gnd i/o 149 i/o 148 i/o 147 i/o 146 i/o 145 i/o 144 i/o 143 i/o 142 i/o 141 i/o 140 nc gnd ultra37000 ? cpld family document #: 38-03007 rev. ** page 42 of 67 pin configurations [19] (continued) 256-ball pbga (bg256) top view 1234567891011121314151617181920 a gnd i/o 21 nc i/o 16 i/o 12 i/o 9 i/o 7 i/o 4 i/o 0 i/o 190 i/o 189 i/o 186 i/o 182 nc i/o 178 i/o 175 nc nc i/o 169 i/o 168 a b i/o 23 i/o 20 i/o 19 i/o 18 i/o 15 i/o 11 i/o 8 i/o 5 i/o 1 i/o 191 i/o 187 i/o 185 i/o 181 nc nc i/o 174 i/o 171 i/o 170 nc i/o 166 b c nc nc i/o 22 nc i/o 17 i/o 14 i/o 10 i/o 6 i/o 2 nc i/o 188 i/o 184 i/o 180 i/o 179 i/o 176 i/o 173 i/o 172 i/o 167 i/o 165 i/o 162 c d i/o 24 nc nc gnd nc v cco i/o 13 gnd i/o 3 nc v cc i/o 183 gnd i/o 177 v cco nc gnd i/o 164 tdi i/o 160 d e i/o 27 i/o 26 i/o 25 nc i/o 163 i/o 161 i/o 159 i/o 156 e f i/o 30 tck i/o 28 v cco v cco i/o 158 nc i/o 154 f g i/o 33 i/o 32 i/o 31 i/o 29 i/o 157 i/o 155 i/o 153 i/o 152 g h i/o 35 nc i/o 34 gnd gnd gnd gnd gnd gnd gnd gnd i/o 151 i/o 150 i/o 149 h j i/o 39 i/o 38 i/o 37 i/o 36 gnd gnd gnd gnd gnd gnd i/o 148 i/o 147 i/o 146 i/o 145 j k i/o 42 i/o 40 i/o 41 v cc gnd gnd gnd gnd gnd gnd i/o 144 clk 3 /i 4 nc nc k l i/o 43 i/o 44 i/o 45 i/o 46 gnd gnd gnd gnd gnd gnd v cc clk 2 /i 3 i/o 143 nc l m i/o 47 clk 0 /i 0 clk 1 /i 1 i/o 48 gnd gnd gnd gnd gnd gnd i/o 139 i/o 140 i/o 141 i/o 142 m n i/o 49 i/o 50 i/o 51 gnd gnd gnd gnd gnd gnd gnd gnd i/o 136 i/o 137 i/o 138 n p i/o 52 i/o 53 i/o 55 i/o 58 i/o 131 i/o 133 i/o 134 i/o 135 p r i/o 54 i/o 56 i/o 59 v cco v cco i/o 130 nc i/o 132 r t i/o 57 i/o 60 i/o 62 i/o 65 i/o 124 i/o 127 i/o 128 i/o 129 t u i/o 61 i/o 63 i/o 66 gnd i/o 76 v cco i/o 82 gnd i/o 91 v cc i/o 98 i/o 102 gnd i/o 112 v cco nc gnd i/o 123 i/o 122 i/o 126 u v i/o 64 i/o 67 i/o 69 i/o 75 i/o 78 i/o 81 i/o 85 i/o 88 i/o 92 i 2 i/o 97 i/o 101 i/o 105 i/o 109 i/o 113 tdo i/o 11 4 i/o 117 i/o 121 i/o 125 v w i/o 68 i/o 70 i/o 72 i/o 74 i/o 79 i/o 83 i/o 86 i/o 89 i/o 93 i/o 95 i/o 96 i/o 100 i/o 104 i/o 107 i/o 110 nc nc i/o 115 i/o 118 i/o 120 w y i/o 71 i/o 73 i/o 77 tms i/o 80 i/o 84 i/o 87 i/o 90 i/o 94 nc nc i/o 99 i/o 103 i/o 106 i/o 108 i/o 111 nc nc i/o 116 i/o 119 y 1234567891011121314151617181920 ultra37000 ? cpld family document #: 38-03007 rev. ** page 43 of 67 pin configurations [19] (continued) 256-ball fine-pitch bga (bb256) top view 12345678910111213141516 a gnd gnd i/o 26 i/o 24 i/o 20 v cc i/o 11 gnd gnd i/o 186 v cc i/o 177 i/o 172 i/o 167 gnd gnd b gnd i/o 27 i/o 25 i/o 23 i/o 19 i/o 15 i/o 10 gnd gnd i/o 185 i/o 181 i/o 176 i/o 171 i/o 166 i/o 165 gnd c i/o 29 i/o 28 nc i/o 22 i/o 18 i/o 14 i/o 9 i/o 4 i/o 191 i/o 184 i/o 180 i/o 175 i/o 170 nc i/o 163 i/o 164 d i/o 32 i/o 31 i/o 30 nc i/o 17 i/o 13 i/o 8 i/o 3 i/o 190 i/o 183 i/o 179 i/o 174 i/o 169 i/o 160 i/o 161 i/o 162 e i/o 35 i/o 34 i/o 33 i/o 21 i/o 16 i/o 12 i/o 7 i/o 2 i/o 189 v cc i/o 178 i/o 173 i/o 168 i/o 157 i/o 158 i/o 159 fv cc i/o 38 i/o 37 i/o 36 tck v cc i/o 6 i/o 1 i/o 188 i/o 182 v cc tdi i/o 154 i/o 155 i/o 156 v cc g i/o 43 i/o 42 i/o 41 i/o 40 v cc i/o 39 i/o 5 i/o 0 i/o 187 i/o 148 i/o 149 clk 3 /i 4 i/o 150 i/o 151 i/o 152 i/o 153 h gnd gnd i/o 47 i/o 46 clk 0 /i 0 i/o 45 i/o 44 gnd gnd i/o 144 i/o 145 clk 2 /i 3 i/o 146 i/o 147 gnd gnd j gnd gnd i/o 51 i/o 50 nc i/o 49 i/o 48 gnd gnd i/o 140 i/o 141 i 2 i/o 142 i/o 143 gnd gnd k i/o 57 i/o 56 i/o 55 i/o 54 clk 1 /i 1 i/o 53 i/o 52 i/o 91 i/o 96 i/o 101 i/o 135 v cc i/o 136 i/o 137 i/o 138 i/o 139 lv cc i/o 60 i/o 59 i/o 58 tms v cc i/o 86 i/o 92 i/o 97 i/o 102 v cc tdo i/o 132 i/o 133 i/o 134 v cc m i/o 63 i/o 62 i/o 61 i/o 72 i/o 77 i/o 82 v cc i/o 93 i/o 98 i/o 103 i/o 108 i/o 11 2 i/o 117 i/o 129 i/o 130 i/o 131 n i/o 66 i/o 65 i/o 64 i/o 73 i/o 78 i/o 83 i/o 87 i/o 94 i/o 99 i/o 104 i/o 109 i/o 11 3 nc i/o 126 i/o 127 i/o 128 p i/o 68 i/o 67 nc i/o 74 i/o79 i/o 84 i/o 88 i/o 95 i/o 100 i/o 105 i/o 110 i/o 11 4 i/o 118 nc i/o 124 i/o 125 r gnd i/o 69 i/o 70 i/o 75 i/o 80 i/o 85 i/o 89 gnd gnd i/o 106 i/o 111 i/o 11 5 i/o 119 i/o 121 i/o 123 gnd t gnd gnd i/o 71 i/o 76 i/o 81 v cc i/o 90 gnd gnd i/o 107 v cc i/o 11 6 i/o 120 i/o 122 gnd gnd ultra37000 ? cpld family document #: 38-03007 rev. ** page 44 of 67 pin configurations [19] (continued) 352-lead bga (bg352) top view 1234567891011121314151617181920212223242526 agndgndi/o 19 i/o 15 i/o 13 i/o 34 i/o 31 i/o 28 i/o 25 i/o 10 i/o 7 i/o 4 i/o 1 i/o 263 i/o 260 i/o 257 i/o 254 i/o 239 i/o 237 i/o 232 i/o 229 i/o 250 i/o 248 i/o 244 gnd gnd b gnd nc i/o 18 i/o 17 i/o 14 i/o 35 i/o 32 i/o 29 i/o 26 i/o 11 i/o 8 i/o 5 i/o 2 v cc i/o 261 i/o 258 i/o 255 i/o 252 i/o 234 i/o 231 i/o 228 i/o 249 i/o 246 i/o 245 i/o 240 gnd ci/o 23 i/o 38 i/o 37 i/o 16 i/o 12 i/o 33 i/o 30 i/o 27 i/o 24 i/o 9 i/o 6 i/o 3 i/o 0 i/o 262 i/o 259 i/o 256 i/o 253 i/o 238 i/o 235 i/o 233 i/o 230 i/o 251 i/o 247 i/o 225 i/o 224 i/o 227 di/o 39 i/o 40 i/o 36 nc nc i/o 21 i/o 20 v cco v cco nc gnd gnd v cco v cco gnd gnd nc v cco v cco i/o 236 i/o 243 nc nc i/o 226 i/o 222 i/o 223 ei/o 42 tck i/o 41 nc nc tdi i/o 221 i/o 220 fi/o 45 i/o 44 i/o 43 i/o 22 i/o 242 i/o 219 i/o 218 i/o 217 gi/o 48 i/o 47 i/o 46 i/o 63 i/o 241 i/o 216 i/o 215 i/o 214 hi/o 49 i/o 50 i/o 51 v cco v cco i/o 211 i/o 212 i/o 213 ji/o 52 i/o 53 i/o 54 v cco v cco i/o 208 i/o 209 i/o 210 ki/o 55 i/o 56 i/o 57 nc nc i/o 205 i/o 206 i/o 207 li0i/o 59 i/o 58 gnd gnd gnd gnd gnd gnd gnd gnd i/o 204 i4 i/o 197 mi/o 61 i/o 60 i1 gnd gnd gnd gnd gnd gnd gnd gnd i3 i/o 203 i/o 202 ni/o 64 v cc i/o 62 v cco gnd gnd gnd gnd gnd gnd v cco i/o 201 i/o 200 i/o 199 pi/o 65 i/o 66 i/o 67 v cco gnd gnd gnd gnd gnd gnd v cco i/o 196 v cc i/o 198 ri/o 68 i/o 69 i/o 70 gnd gnd gnd gnd gnd gnd gnd gnd i/o 193 i/o 194 i/o 195 ti/o 71 i/o 84 i/o 85 gnd gnd gnd gnd gnd gnd gnd gnd i/o 178 i/o 179 i/o 192 ui/o 88 i/o 87 i/o 86 nc nc i/o 177 i/o 176 i/o 175 vi/o 91 i/o 90 i/o 89 v cco v cco i/o 174 i/o 173 i/o 172 wi/o 94 i/o 93 i/o 92 v cco v cco i/o 171 i/o 170 i/o 169 yi/o 95 i/o 72 i/o 73 i/o 110 i/o 153 i/o 190 i/o 191 i/o 168 aa i/o 74 i/o 75 i/o 76 i/o 111 i/o 152 i/o 187 i/o 188 i/o 189 ab i/o 77 i/o 78 i/o 79 n/c nc i/o 184 i/o 185 i/o 186 ac i/o 81 i/o 80 i/o 108 n/c nc i/o 112 i/o 113 v cco v cco nc gnd gnd v cco v cco gnd gnd nc v cco v cco i/o 150 i/o 151 nc nc i/o 155 i/o 183 i/o 182 ad i/o 109 i/o 82 i/o 83 i/o 117 i/o 97 i/o 100 i/o 102 i/o 105 i/o 120 i/o 123 i/o 126 i/o 129 i2 i/o 133 i/o 136 i/o 139 i/o 142 i/o 157 i/o 159 i/o 161 i/o 163 i/o 166 i/o 146 i/o 180 i/o 181 i/o 154 ae gnd nc i/o 115 i/o 116 i/o 119 i/o 98 i/o 101 i/o 103 i/o 106 i/o 121 i/o 124 i/o 127 v cc i/o 130 i/o 134 i/o 137 i/o 140 i/o 143 i/o 160 i/o 162 i/o 165 i/o 144 i/o 147 i/o 148 nc gnd af gnd gnd i/o 114 i/o 118 i/o 96 i/o 99 tms i/o 104 i/o 107 i/o 122 i/o 125 i/o 128 i/o 131 i/o 132 i/o 135 i/o 138 i/o 141 i/o 156 i/o 158 tdo i/o 164 i/o 167 i/o 145 i/o 149 gnd gnd ultra37000 ? cpld family document #: 38-03007 rev. ** page 45 of 67 pin configurations [19] (continued) 400-ball fine-pitch bga (bb400) top view a gndgndnci/o 17 i/o 16 i/o 14 i/o 29 v cc i/o 11 gnd gnd i/o 257 v cc i/o 239 i/o 233 i/o 232 i/o 230 nc gnd gnd b gnd gnd gnd nc i/o 15 i/o 13 i/o 28 v cc i/o 10 gnd gnd i/o 256 v cc i/o 238 i/o 231 i/o 229 nc gnd gnd gnd c nc gnd gnd gnd i/o 20 i/o 12 i/o 27 v cc i/o 9 gnd gnd i/o 255 v cc i/o 237 i/o 228 i/o 245 gnd gnd gnd nc di/o 44 nc gnd i/o 21 i/o 19 i/o 18 i/o 26 i/o 25 i/o 8 gnd gnd i/o 254 i/o 235 i/o 236 i/o 251 i/o 244 i/o 243 gnd nc i/o 227 ei/o 46 i/o 43 i/o 23 i/o 22 nc i/o 35 i/o 34 i/o 24 i/o 7 i/o 4 i/o 263 i/o 253 i/o 234 i/o 250 i/o 248 nc i/o 241 i/o 242 i/o 225 i/o 226 fi/o 47 i/o 45 i/o 42 i/o 41 i/o 40 nc i/o 33 i/o 32 i/o 6 i/o 3 i/o 262 i/o 252 i/o 249 i/o 247 i/o 220 i/o 221 i/o 240 i/o 222 i/o 223 i/o 224 gi/o 53 i/o 52 i/o 51 i/o 50 i/o 39 i/o 38 i/o 37 i/o 31 i/o 5 i/o 2 i/o 261 v cc i/o 246 i/o 217 i/o 218 i/o 219 i/o 212 i/o 213 i/o 214 i/o 215 hv cc v cc v cc i/o 49 i/o 48 i/o 36 tck v cc i/o 30 i/o 1 i/o 259 i/o 260 v cc tdi i/o 216 i/o 210 i/o 211 v cc v cc v cc ji/o 59 i/o 58 i/o 57 i/o 56 i/o 55 i/o 54 v cc i/o 62 i/o 60 i/o 0 i/o 258 i/o 202 i/o 203 clk 3 /i 4 i/o 204 i/o 205 i/o 206 i/o 207 i/o 208 i/o 209 k gnd gnd gnd gnd i/o 65 i/o 64 clk 0 /i 0 i/o 63 i/o 61 gnd gnd i/o 198 i/o 199 clk 2 /i 3 i/o 200 i/o 201 gnd gnd gnd gnd l gnd gnd gnd gnd i/o 69 i/o 68 nc i/o 67 i/o 66 gnd gnd i/o 193 i/o 195 i 2 i/o 196 i/o 197 gnd gnd gnd gnd mi/o 89 i/o 88 i/o 87 i/o 86 i/o 85 i/o 84 clk 1 /i 1 i/o 71 i/o 70 i/o 126 i/o 132 i/o 192 i/o 194 v cc i/o 174 i/o 175 i/o 176 i/o 177 i/o 178 i/o 179 nv cc v cc v cc i/o 91 i/o 90 i/o 72 tms v cc i/o 128 i/o 127 i/o 133 i/o 162 v cc tdo i/o 180 i/o 168 i/o 169 v cc v cc v cc pi/o 95 i/o 94 i/o 93 i/o 92 i/o 75 i/o 74 i/o 73 i/o 114 v cc i/o 129 i/o 134 i/o 137 i/o 163 i/o 181 i/o 182 i/o 183 i/o 170 i/o 171 i/o 172 i/o 173 ri/o 80 i/o 79 i/o 78 i/o 108 i/o 77 i/o 76 i/o 115 i/o 117 i/o 120 i/o 130 i/o 135 i/o 138 i/o 164 i/o 165 nc i/o 184 i/o 185 i/o 186 i/o 189 i/o 191 ti/o 82 i/o 81 i/o 110 i/o 109 nc i/o 116 i/o 118 i/o 102 i/o 121 i/o 131 i/o 136 i/o 139 i/o 156 i/o 166 i/o 167 nc i/o 154 i/o 155 i/o 187 i/o 190 ui/o 83 nc gnd i/o 111 i/o 112 i/o 119 i/o 104 i/o 103 i/o 122 gnd gnd i/o 140 i/o 157 i/o 158 i/o 150 i/o 151 i/o 153 gnd nc i/o 188 v nc gnd gnd gnd i/o 113 i/o 96 i/o 105 v cc i/o 123 gnd gnd i/o 141 v cc i/o 159 i/o144 i/o 152 gnd gnd gnd nc w gnd gnd gnd nc i/o 97 i/o 99 i/o 106 v cc i/o 124 gnd gnd i/o 142 v cc i/o 160 i/o 145 i/o 147 nc gnd gnd gnd y gndgndnci/o 98 i/o 100 i/o 101 i/o 107 v cc i/o 125 gnd gnd i/o 143 v cc i/o 161 i/o 146 i/o 148 i/o 149 nc gnd gnd ultra37000 ? cpld family document #: 38-03007 rev. ** page 46 of 67 ordering information 5.0v ordering information macro- cells speed (mhz) ordering code package name package type operating range 32 200 cy37032p44-200ac a44 44-lead thin quad flat pack commercial cy37032p44-200jc j67 44-lead plastic leaded chip carrier 154 cy37032p44-154ac a44 44-lead thin quad flat pack commercial cy37032p44-154jc j67 44-lead plastic leaded chip carrier cy37032p44-154ai a44 44-lead thin quad flat pack industrial cy37032p44-154ji j67 44-lead plastic leaded chip carrier 125 cy37032p44-125ac a44 44-lead thin quad flat pack commercial cy37032p44-125jc j67 44-lead plastic leaded chip carrier cy37032p44-125ai a44 44-lead thin quad flat pack industrial cy37032p44-125ji j67 44-lead plastic leaded chip carrier c y 3 7 5 1 2 v p 4 0 0 - 8 3 b b c cypress semiconductor id family type 37 = ultra37000 family macrocell density 32 = 32 macrocells 256 = 256 macrocells 64 = 64 macrocells 384 = 384 macrocells 128 = 128 macrocells 512 = 512 macrocells 192 = 192 macrocells speed 125 = 125 mhz 200 = 200 mhz 100 = 100 mhz 167 = 167 mhz 83 = 83 mhz 154 = 154 mhz 66 = 66 mhz 143 = 143 mhz package type a = thin quad flat pack (tqfp) u = ceramic quad flat pack (cqfp) n = plastic quad flat pack (pqfp) nt = thermally enhanced plastic quad flat pack (eqfp) j = plastic leaded chip carrier (plcc) y = ceramic leaded chip carrier (clcc) bg = ball grid array (bga) ba = fine-pitch ball grid array (fbga) 0.8mm lead pitch bb = fine-pitch ball grid array (fbga) 1.0mm lead pitch operating conditions commercial 0 c to +70 c industrial -40 c to +85 c military -55 c to +125 c operating reference voltage v = 3.3v supply voltage (5.0v if not specified) pin count p44 = 44 leads p48 = 48 leads p84 = 84 leads p100 = 100 leads p160 = 160 leads p208 = 208 leads p256 = 256 leads p352 = 352 leads p400 = 400 leads ultra37000 ? cpld family document #: 38-03007 rev. ** page 47 of 67 64 200 cy37064p44-200ac a44 44-lead thin quad flat pack commercial cy37064p44-200jc j67 44-lead plastic leaded chip carrier cy37064p84-200jc j83 84-lead plastic leaded chip carrier cy37064p100-200ac a100 100-lead thin quad flat pack 154 cy37064p44-154ac a44 44-lead thin quad flat pack commercial cy37064p44-154jc j67 44-lead plastic leaded chip carrier cy37064p84-154jc j83 84-lead plastic leaded chip carrier cy37064p100-154ac a100 100-lead thin quad flat pack cy37064p44-154ai a44 44-lead thin quad flat pack industrial cy37064p44-154ji j67 44-lead plastic leaded chip carrier cy37064p84-154ji j83 84-lead plastic leaded chip carrier cy37064p100-154ai a100 100-lead thin quad flat pack 5962-9951902qya y67 44-lead ceramic leadless chip carrier military 125 cy37064p44-125ac a44 44-lead thin quad flat pack commercial cy37064p44-125jc j67 44-lead plastic leaded chip carrier cy37064p84-125jc j83 84-lead plastic leaded chip carrier cy37064p100-125ac a100 100-lead thin quad flat pack cy37064p44-125ai a44 44-lead thin quad flat pack industrial cy37064p44-125ji j67 44-lead plastic leaded chip carrier cy37064p84-125ji j83 84-lead plastic leaded chip carrier cy37064p100-125ai a100 100-lead thin quad flat pack 5962-9951901qya y67 44-lead ceramic leadless chip carrier military 128 167 cy37128p84-167jc j83 84-lead plastic leaded chip carrier commercial cy37128p100-167ac a100 100-lead thin quad flat pack cy37128p160-167ac a160 160-lead thin quad flat pack 125 cy37128p84-125jc j83 84-lead plastic leaded chip carrier commercial cy37128p100-125ac a100 100-lead thin quad flat pack cy37128p160-125ac a160 160-lead thin quad flat pack cy37128p84-125ji j83 84-lead plastic leaded chip carrier industrial cy37128p100-125ai a100 100-lead thin quad flat pack cy37128p160-125ai a160 160-lead thin quad flat pack 5962-9952102qya y84 84-lead ceramic leaded chip carrier military 100 cy37128p84-100jc j83 84-lead plastic leaded chip carrier commercial cy37128p100-100ac a100 100-lead thin quad flat pack cy37128p160-100ac a160 160-lead thin quad flat pack cy37128p84-100ji j83 84-lead plastic leaded chip carrier industrial cy37128p100-100ai a100 100-lead thin quad flat pack cy37128p160-100ai a160 160-lead thin quad flat pack 5962-9952101qya y84 84-lead ceramic leaded chip carrier military 5.0v ordering information (continued) macro- cells speed (mhz) ordering code package name package type operating range ultra37000 ? cpld family document #: 38-03007 rev. ** page 48 of 67 192 154 cy37192p160-154ac a160 160-lead thin quad flat pack commercial 125 cy37192p160-125ac a160 160-lead thin quad flat pack commercial cy37192p160-125ai a160 160-lead thin quad flat pack industrial 83 cy37192p160-83ac a160 160-lead thin quad flat pack commercial cy37192p160-83ai a160 160-lead thin quad flat pack industrial 256 154 cy37256p160-154ac a160 160-lead thin quad flat pack commercial cy37256p208-154nc n208 208-lead plastic quad flat pack cy37256p256-154bgc bg256 256-lead ball grid array 125 cy37256p160-125ac a160 160-lead thin quad flat pack commercial cy37256p208-125nc n208 208-lead plastic quad flat pack cy37256p256-125bgc bg256 256-lead ball grid array cy37256p160-125ai a160 160-lead thin quad flat pack industrial cy37256p208-125ni n208 208-lead plastic quad flat pack cy37256p256-125bgi bg256 256-lead ball grid array 5962-9952302qzc u162 160-lead ceramic quad flat pack military 83 cy37256p160-83ac a160 160-lead thin quad flat pack commercial cy37256p208-83nc n208 208-lead plastic quad flat pack cy37256p256-83bgc bg256 256-lead ball grid array cy37256p160-83ai a160 160-lead thin quad flat pack industrial cy37256p208-83ni n208 208-lead plastic quad flat pack cy37256p256-83bgi bg256 256-lead ball grid array 5962-9952301qzc u162 160-lead ceramic quad flat pack military 384 125 cy37384p208-125nc n208 208-lead plastic quad flat pack commercial cy37384p256-125bgc bg256 256-lead ball grid array 83 cy37384p208-83nc n208 208-lead plastic quad flat pack commercial cy37384p256-83bgc bg256 256-lead ball grid array cy37384p208-83ni n208 208-lead plastic quad flat pack industrial cy37384p256-83bgi bg256 256-lead ball grid array 5.0v ordering information (continued) macro- cells speed (mhz) ordering code package name package type operating range ultra37000 ? cpld family document #: 38-03007 rev. ** page 49 of 67 512 125 cy37512p208-125nc n208 208-lead plastic quad flat pack commercial cy37512p256-125bgc bg256 256-lead ball grid array cy37512p352-125bgc bg352 352-lead ball grid array 100 cy37512p208-100nc n208 208-lead plastic quad flat pack commercial cy37512p256-100bgc bg256 256-lead ball grid array cy37512p352-100bgc bg352 352-lead ball grid array cy37512p208-100ni n208 208-lead plastic quad flat pack industrial CY37512P256-100BGI bg256 256-lead ball grid array cy37512p352-100bgi bg352 352-lead ball grid array 5962-9952502qzc u208 208-lead ceramic quad flat pack military 83 cy37512p208-83nc n208 208-lead plastic quad flat pack commercial cy37512p256-83bgc bg256 256-lead ball grid array cy37512p352-83bgc bg352 352-lead ball grid array cy37512p208-83ni n208 208-lead plastic quad flat pack industrial cy37512p256-83bgi bg256 256-lead ball grid array cy37512p352-83bgi bg352 352-lead ball grid array 5962-9952501qzc u208 208-lead ceramic quad flat pack military 5.0v ordering information (continued) macro- cells speed (mhz) ordering code package name package type operating range 3.3v ordering information macro- cells speed (mhz) ordering code package name package type operating range 32 143 cy37032vp44-143ac a44 44-lead thin quad flat pack commercial cy37032vp44-143jc j67 44-lead plastic leaded chip carrier cy37032vp48-143bac ba50 48-lead fine pitch ball grid array 100 cy37032vp44-100ac a44 44-lead thin quad flat pack commercial cy37032vp44-100jc j67 44-lead plastic leaded chip carrier cy37032vp48-100bac ba50 48-lead fine pitch ball grid array cy37032vp44-100ai a44 44-lead thin quad flat pack industrial cy37032vp44-100ji j67 44-lead plastic leaded chip carrier cy37032vp48-100bai ba50 48-lead fine pitch ball grid array ultra37000 ? cpld family document #: 38-03007 rev. ** page 50 of 67 64 143 cy37064vp44-143ac a44 44-lead thin quad flatpack commercial cy37064vp44-143jc j67 44-lead plastic leaded chip carrier cy37064vp48-143bac ba50 48-lead fine-pitch ball grid array cy37064vp84-143jc j83 84-lead plastic leaded chip carrier cy37064vp100-143ac a100 100-lead thin quad flatpack cy37064vp100-143bbc bb100 100-lead fine-pitch ball grid array 100 cy37064vp44-100ac a44 44-lead thin quad flatpack commercial cy37064vp44-100jc j67 44-lead plastic leaded chip carrier cy37064vp48-100bac ba50 48-lead fine-pitch ball grid array cy37064vp84-100jc j83 84-lead plastic leaded chip carrier cy37064vp100-100ac a100 100-lead thin quad flatpack cy37064vp100-100bbc bb100 100-lead fine-pitch ball grid array cy37064vp44-100ai a44 44-lead thin quad flatpack industrial cy37064vp44-100ji j67 44-lead plastic leaded chip carrier cy37064vp48-100bai ba50 48-lead fine-pitch ball grid array cy37064vp84-100ji j83 84-lead plastic leaded chip carrier cy37064vp100-100bbi bb100 100-lead fine-pitch ball grid array cy37064vp100-100ai a100 100-lead thin quad flatpack 5962-9952001qya y67 44-lead ceramic leaded chip carrier military 128 125 cy37128vp84-125jc j83 84-lead plastic leaded chip carrier commercial cy37128vp100-125ac a100 100-lead thin quad flat pack cy37128vp100-125bbc bb100 100-lead fine-pitch ball grid array cy37128vp160-125ac a160 160-lead thin quad flat pack 83 cy37128vp84-83jc j83 84-lead plastic leaded chip carrier commercial cy37128vp100-83ac a100 100-lead thin quad flat pack cy37128vp100-83bbc bb100 100-lead fine-pitch ball grid array cy37128vp160-83ac a160 160-lead thin quad flat pack cy37128vp84-83ji j83 84-lead plastic leaded chip carrier industrial cy37128vp100-83ai a100 100-lead thin quad flat pack cy37128vp100-83bbi bb100 100-lead fine-pitch ball grid array cy37128vp160-83ai a160 160-lead thin quad flat pack 5962-9952201qya y84 84-lead ceramic leaded chip carrier military 192 100 cy37192vp160-100ac a160 160-lead thin quad flat pack commercial 66 cy37192vp160-66ac a160 160-lead thin quad flat pack commercial cy37192vp160-66ai a160 160-lead thin quad flat pack industrial 3.3v ordering information (continued) macro- cells speed (mhz) ordering code package name package type operating range ultra37000 ? cpld family document #: 38-03007 rev. ** page 51 of 67 in-system reprogrammable, isr, ultra37000, warp , warp professional, and warp enterprise are trademarks of cypress semiconductor corporation. viewdraw and speedwave are trademarks of viewlogic. windows is a registered trademark of microsoft corporation. 256 100 cy37256vp160-100ac a160 160-lead thin quad flat pack commercial cy37256vp208-100nc n208 208-lead plastic quad flat pack cy37256vp256-100bgc bg256 256-lead ball grid array cy37256vp256-100bbc bb256 256-lead fine-pitch ball grid array 66 cy37256vp160-66ac a160 160-lead thin quad flat pack commercial cy37256vp208-66nc n208 208-lead plastic quad flat pack cy37256vp256-66bgc bg256 256-lead ball grid array cy37256vp256-66bbc bb256 256-lead fine-pitch ball grid array cy37256vp160-66ai a160 160-lead thin quad flat pack industrial cy37256vp256-66bgi bg256 256-lead ball grid array cy37256vp256-66bbi bb256 256-lead fine-pitch ball grid array 5962-9952401qzc u162 160-lead ceramic quad flat pack military 384 83 cy37384vp208-83nc n208 208-lead plastic quad flat pack commercial cy37384vp256-83bgc bg256 256-lead ball grid array 66 cy37384vp208-66nc n208 208-lead plastic quad flat pack commercial cy37384vp256-66bgc bg256 256-lead ball grid array cy37384vp208-66ni n208 208-lead plastic quad flat pack industrial cy37384vp256-66bgi bg256 256-lead ball grid array 512 83 cy37512vp208-83nc n208 208-lead plastic quad flat pack commercial cy37512vp256-83bgc bg256 256-lead ball grid array cy37512vp352-83bgc bg352 352-lead ball grid array cy37512vp400-83bbc bb400 400-lead fine-pitch ball grid array 66 cy37512vp208-66nc n208 208-lead plastic quad flat pack commercial cy37512vp256-66bgc bg256 256-lead ball grid array cy37512vp352-66bgc bg352 352-lead ball grid array cy37512vp400-66bbc bb400 400-lead fine-pitch ball grid array cy37512vp208-66ni n208 208-lead plastic quad flat pack industrial cy37512vp256-66bgi bg256 256-lead ball grid array cy37512vp352-66bgi bg352 352-lead ball grid array cy37512vp400-66bbi bb400 400-lead fine-pitch ball grid array 5962-9952601qzc u208 208-lead ceramic quad flat pack military 3.3v ordering information (continued) macro- cells speed (mhz) ordering code package name package type operating range ultra37000 ? cpld family document #: 38-03007 rev. ** page 52 of 67 package diagrams 44-lead thin plastic quad flat pack a44 51-85064-b 44-lead plastic leaded chip carrier j67 51-85003-a ultra37000 ? cpld family document #: 38-03007 rev. ** page 53 of 67 package diagrams (continued) 44-pin ceramic leaded chip carrier y67 51-80014 ultra37000 ? cpld family document #: 38-03007 rev. ** page 54 of 67 package diagrams (continued) 48-ball (7.0 mm x 7.0 mm x 1.1 mm, 0.80 pitch) thin bga ba50 51-85109-a ultra37000 ? cpld family document #: 38-03007 rev. ** page 55 of 67 package diagrams (continued) 84-lead plastic leaded chip carrier j83 51-85006-a ultra37000 ? cpld family document #: 38-03007 rev. ** page 56 of 67 package diagrams (continued) 84-pin ceramic leaded chip carrier y84 51-80095-a ultra37000 ? cpld family document #: 38-03007 rev. ** page 57 of 67 package diagrams (continued) 100-pin thin plastic quad flat pack (tqfp) a100 51-85048-b ultra37000 ? cpld family document #: 38-03007 rev. ** page 58 of 67 package diagrams (continued) 100-ball thin ball grid array (11 x 11 x 1.4 mm) bb100 51-85107 ultra37000 ? cpld family document #: 38-03007 rev. ** page 59 of 67 package diagrams (continued) 160-pin thin plastic quad flat pack (tqfp) a160 51-85049-a ultra37000 ? cpld family document #: 38-03007 rev. ** page 60 of 67 package diagrams (continued) 160-lead ceramic quad flatpack (cavity up) u162 51-80106 ultra37000 ? cpld family document #: 38-03007 rev. ** page 61 of 67 package diagrams (continued) 208-lead plastic quad flatpack n208 51-85069-b ultra37000 ? cpld family document #: 38-03007 rev. ** page 62 of 67 package diagrams (continued) 208-lead ceramic quad flatpack (cavity up) u208 51-80105 51-85097 51-85108-a 51-85103 51-85111-a ** 106272 04/18/01 szv change from spec number: 38-00475 to 38-03007 |
Price & Availability of CY37512P256-100BGI
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